1. Technical Field
This disclosure relates to semiconductor memory devices, and more particularly, to a circuit, device, and method for performing a partial array refresh operation.
2. Description of the Related Art
Recently, an internal voltage generating circuit for maintaining an internal power voltage at a predetermined level independent of an external power voltage has been used in semiconductor memory devices operating in the region of 3V to 6V to improve properties such as high-speed operation and low operating current. With the increased operating current drawn by semiconductor products that are designed to operate at a low supply voltage of 3.3V using an external voltage (EVC), semiconductor products solving these problems using an internal voltage generating circuit have been favored.
In a memory circuit, the internal voltage generating circuit includes an internal voltage generating circuit that is configured to supply an internal voltage to the memory array and an internal voltage generating circuit that is configured to supply an internal voltage to the peripheral circuits associated with the memory array.
The internal voltage generating circuit for the memory array supplies a predetermined voltage required for storing data in a memory array bank or for reading data from the memory array bank.
The internal voltage generating circuit for the peripheral circuits supplies a predetermined voltage required for operating peripheral circuits of an associated memory array bank, but not the memory array bank itself. For example, peripheral circuits may include decoders, input buffers, output buffers, and input and output lines.
The internal voltage generating circuit for the peripheral circuits includes a standby internal voltage generating circuit that operates continually after power is turned on and an active internal voltage generating circuit that operates only when the corresponding memory bank is enabled.
FIG. 9 is a simplified block diagram illustrating a conventional refresh operation in a semiconductor memory device. In this conventional refresh operation, it may be assumed that a memory device 100 has a memory cell array that can be divided into four memory banks A, B, C and D, each bank having N word lines. Thus, in general, N refresh operations are concurrently performed on each of the four memory banks A, B, C and D. Each of the N word lines must be supplied with the appropriate voltage in order to perform read and write operations.
Embodiments of the invention address this and other disadvantages of the conventional art.